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F81216AD
F81216AD
LPC to 4 UART + 9-bit Protocol
Release Date: July, 2008 Version: V0.20P
F81216AD.
July, 2008 V0.20P
F81216AD
F81216AD Datasheet Revision History
Version V0.20P Date 2008/7/24 Page Revision History Release Version
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Fintek for any damages resulting from such improper use or sales.
F81216AD.
July, 2008 V0.20P
F81216AD
Table of Content
1. General Description.................................................................................................................................1 2. Feature List..............................................................................................................................................1 3. Pin Configuration ....................................................................................................................................2 4. Pin Description........................................................................................................................................3 4.1 ISA/LPC Interface ................................................................................................................................. 3 4.2 UART Interface...................................................................................................................................... 4 4.3 Power ..................................................................................................................................................... 7 5. Functional Description ............................................................................................................................8 5.1 LPC Interface ...................................................................................................................................... 8 5.2 UART.................................................................................................................................................. 8 5.3 IR Function ....................................................................................................................................... 13 5.4 Watch Dog Timer Function............................................................................................................... 13 5.5 Serial IRQ ......................................................................................................................................... 14 6. Register Description......................................................................................................................17 6.1. Global Control Registers............................................................................................................... 19 6.2. UART1 Registers (CR00) ............................................................................................................. 21 6.3. UART2 Registers (CR01) ............................................................................................................. 25 6.4. UART3 Registers (CR02) ............................................................................................................. 28 6.5. UART4 Registers (CR03) ............................................................................................................. 31 6.6. Watchdog Timer Registers (CR08) ............................................................................................... 34 7. Electron Characteristic .......................................................................................................................36 7.1 Absolute Maximum Ratings ............................................................................................................. 36 7.2 DC Characteristics ............................................................................................................................... 36 8. Ordering Information .........................................................................................................................37 9. Package Dimensions ..........................................................................................................................38 10. Application Circuit ...........................................................................................................................39
F81216AD.
July, 2008 V0.20P
F81216AD
1. General Description
The F81216AD mainly provides 3 pure UART ports and one UART+ IR port through LPC. Each UART includes 16-byte send/receive FIFO, a programmable baud rate One watch dog timer is provided for system controlling and the time interval can be programmed by register or hardware power on setting pin. One clock 24/48MHz input is necessary, and default is 24MHz. Powered by 3.3V voltage, the F81216AD is in the small 48pin LQFP package (7mm x 7mm). generator, complete modem control capability and an interrupt system.
2. Feature List
Supports LPC interface Totally provides 4 UART (16550 asynchronous) ports 3 Pure UART 1 UART+IR 1 watch dog timer with WDTOUT# signal Support 9-bit protocol 1 frequency input 24/48MHz Powered by 3Vcc Operation current under 10mA 48-LQFP(7mm x 7mm)
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3. Pin Configuration
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4. Pin Description
I/O8t5V-d100 I/O12t I/OD12 PCI5V OUT12 OD12 INt INt5V INts INts5V P - TTL level bi-directional pin with 8 mA source-sink capability, 5V tolerance, pull-down 100K ohms - TTL level bi-directional pin with 12 mA source-sink capability - TTL level bi-directional pin, Open-drain outpu with 12 mA sink capability - bi-direction pin, slew rate control, 5V tolerance. - Output pin with 12 mA source-sink capability - Open-drain output pin with 12 mA sink capability - TTL level input pin - TTL level input pin and 5V tolerance. - TTL level input pin and schmitt trigger - TTL level input pin and Schmitt trigger, 5V tolerance. - Power
4.1 ISA/LPC Interface
Pin No. 1 2 Pin Name PCIRST# WDT_OUT# Type INts OD12 Description System PCI reset active low. Watch dog timer output. When pin 24 power on setting
PS_WDT=0(default), Watch Dog timer time interval setting is programmed by register. Once power on setting PS_WDT=1, watch dog timer time interval will be fixed to 10 sec. 4~7 LPC_LAD[3:0] PCI5V When in LPC mode, these signal lines communicate address, control, and data information over the LPC bus between a host and a peripheral. 8 9 LCLK FRAME# INts5V INts5V In LPC mode, this pin acts as PCI clock input. In LPC mode, indicates start of a new cycle or termination of a broken cycle. 10 12 SERIRQ CLKIN PCI5V INt5V In LPC mode, Serial IRQ input/Output. Clock Input
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4.2 UART Interface
Pin No. 13 14 Pin Name CTS4# DSR4# Type INt5V INt5V Description Clear To Send is the modem control input. Data Set Ready. An active low signal indicates the modem or data set is ready to establish a communication link and transfer data to the UART. 15 RTS4# I/O8t5V-d100 UART 4 Request To Send. An active low signal informs the modem or data set that the controller is ready to send data. 16 DTR4# I/O8t5V-d100 UART 4 Data Terminal Ready. An active low signal informs the modem or data set that controller is ready to communicate. 17 SIN4 INt5V Serial Input. Used to receive serial data through the
communication link. 18 SOUT4 I/O8t5V-d100 UART 4 Serial Output. Used to transmit serial data out to the communication link. PS_2E8_IRQD Power setting pin to define the IRQD index. Default PS_2E8_IRQD = 0, IRQF index is programmed by register. If PS_2E8_IRQD = 1, setting IRQF index to 0x2E8. 19 DCD4# INt5V Data Carrier Detect. An active low signal indicates the
modem or data set has detected a data carrier. 20 RI4# INt5V Ring Indicator. An active low signal indicates that a ring
signal is being received from the modem or data set. 21 22 CTS3# DSR3# INt5V INt5V Clear To Send is the modem control input. Data Set Ready. An active low signal indicates the modem or data set is ready to establish a communication link and transfer data to the UART. 23 RTS3# I/O8t5V-d100 UART 3 Request To Send. An active low signal informs the modem or data set that the controller is ready to send data. PS_CONF_KE Y0 24 DTR3# I/O8t5V-d100 Power on configuration setting pin. As for detail description, please refer to register description. UART 3 Data Terminal Ready. An active low signal informs the modem or data set that controller is ready to communicate. PS_WDT Power on setting pin to enable the watch dog timer. Default PS_WDT=0, WDT time programmed by register. When PS_WDT=1, WDT time is defined as 10 sec.
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25 SIN3 INt5V Serial Input. Used to receive serial data through the communication link. 26 SOUT3 I/O8t5V-d100 UART 3 Serial Output. Used to transmit serial data out to the communication link. PS_3E8_IRQC Power setting pin to define the IRQC index. Default PS_3E8_IRQC = 0, IRQF index is programmed by register. If PS_3E8_IRQC = 1, setting IRQC index to 0x3E8. 27 DCD3# INt5V Data Carrier Detect. An active low signal indicates the
modem or data set has detected a data carrier. 28 RI3# INt5V Ring Indicator. An active low signal indicates that a ring
signal is being received from the modem or data set. 31 32 CTS2# DSR2# INt5V INt5V Clear To Send is the modem control input. Data Set Ready. An active low signal indicates the modem or data set is ready to establish a communication link and transfer data to the UART. 33 RTS2# I/O8t5V-d100 UART 2 Request To Send. An active low signal informs the modem or data set that the controller is ready to send data. PS_CONF_KE Y1 34 DTR2# I/O8t5V-d100 Power on configuration setting pin. As for detail description, please refer to register description. UART 2 Data Terminal Ready. An active low signal informs the modem or data set that controller is ready to communicate. PS_2E0_IRQB Power setting pin to define the IRQB index. Default PS_2E0_IRQB = 0, IRQB index is programmed by register. If PS_2E0_IRQB = 1, setting IRQB index to 0x2E0. 35 SIN2 INt5V Serial Input. Used to receive serial data through the
communication link. 36 SOUT2 I/O8t5V-d100 UART 2 Serial Output. Used to transmit serial data out to the communication link. PS_2F8_IRQB Power setting pin to define the IRQB index. Default PS_2F8_IRQB = 0, IRQB index is programmed by register. If PS_2F8_IRQB = 1, setting IRQB index to 0x2F8.
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37 DCD2# INt5V Data Carrier Detect. An active low signal indicates the modem or data set has detected a data carrier. 38 RI2# INt5V Ring Indicator. An active low signal indicates that a ring
signal is being received from the modem or data set. 39 40 CTS1# DSR1# INt5V INt5V Clear To Send is the modem control input. Data Set Ready. An active low signal indicates the modem or data set is ready to establish a communication link and transfer data to the UART. 41 RTS1# I/O8t5V-d100 UART 1 Request To Send. An active low signal informs the modem or data set that the controller is ready to send data. PS_CONF_2E Power on configuration setting. Default PS_CONF_2E = 0, setting the configuration to 0x4E. If PS_CONF_2E =1, setting the configuration to 0x2E. 42 DTR1# I/O8t5V-d100 UART 1 Data Terminal Ready. An active low signal informs the modem or data set that controller is ready to communicate. PS_3E0_IRQA Power setting pin to define the IRQA index. Default PS_3E0_IRQA = 0, IRQB index is programmed by register. If PS_3E0_IRQA = 1, setting IRQA index to 0x3E0. 43 SIN1 INt5V Serial Input. Used to receive serial data through the
communication link. 44 SOUT1 I/O8t5V-d100 UART 1 Serial Output. Used to transmit serial data out to the communication link. PS_3F8_IRQA Power setting pin to define the IRQA index. Default PS_3F8_IRQA = 0, IRQA index is programmed by register. If PS_3F8_IRQA = 1, setting IRQA index to 0x3F8. 45 DCD1# INt5V Data Carrier Detect. An active low signal indicates the
modem or data set has detected a data carrier. 46 RI1# INt5V Ring Indicator. An active low signal indicates that a ring
signal is being received from the modem or data set. 47 48 IRRX1 IRTX1 INts5V OUT12 Infrared Receiver input. Infrared Transmitter Output.
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4.3 Power
Pin No. 11,30 3, 29 Pin Name VCC GND Type P P Description 3.3V power supply. Ground.
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5. Functional Description
The F81216AD totally provides 4 UART ports through LPC interface. Among 4 UART ports, one ports can support serial infrared communication. capability and interrupt system. One watch dog timer is provided for system controlling and the time interval can be programmed by register or hardware power on setting pin. This IC needs one clock 24/48MHz input, and default is 24MHz. F81216AD is in 48 pin LQFP Powered by 3.3V voltage, the Besides, each UART includes 16-byte send/receive FIFO, a programmable baud rate generator, completed modem control
5.1
LPC Interface
The F81216AD can support LPC interface serving as a bus interface between host (chipset) and peripheral (I/O chip) by hardware trapping. This interface provides much less pins and more efficient transmission. as below: One control line, namely LPC_FRAME#, which is used by the host to start or stop transfers. No peripherals drive this signal. The LPC_LAD[3:0] bus, which communicates information serially. PCIRST# is an active low reset signal. An additional 33 MHz PCI clock is needed in the F81216AD for synchronization. Interrupt requests are issued through LPC_SERIRQ. The information conveyed is cycle type, cycle direction, chip selection, address, data, and wait states. Data transfer on the LPC bus is serialized over a
4 bit bus. The general characteristics of the interface implemented in F81216AD are listed
5.2
UART
A Universal Asynchronous Receiver/Transmitter (UART) is used to implement serial communication. The F81216AD incorporates four fully function UART compatible with NS16550D. The UART ports perform serial to parallel conversion on receiving characters and parallel to serial conversion on transmitting characters. The controllable characteristics of the
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data transmission are baud rate, number of information bits per character, type of parity checking, number of stop bits and breaking the transmission. The serial format is a start bit, followed by The five to eight data bits, a parity bit(if programmable), and one, one and half, or two stop bits. UART also includes completed modem control capability and interrupt system that may be software trailed to the computing time required to handle the communication link. also has a FIFO mode to reduce the number of interrupts presented to the CPU. there is 16-byte FIFO for both receive and transmit mode. The UART In the UART,
5.2.1 UART Port Register 5.2.1.1 Receiver Buffer Register - Base + 0
Power-on default [7:0] = 0x00h. Bit 7:0 Name RBR[7:0] R/W R The data received . Read only when LCR[7] is 0 Description
5.2.1.2
Transmitter Holding Register - Base + 0
Power-on default [7:0] = 0x00h. Bit 7:0 Name THR[7:0] R/W W Data to be transmitted. Write only when LCR[7] is 0 Description
5.2.1.3
Divisor Latch ( LS ) - Base + 0
Power-on default [7:0] = 0x01h. Bit 7:0 Name DLL[7:0] R/W R/W Description Baud generator divisor low byte. Access only when LCR[7] is 1.
5.2.1.4
Divisor Latch ( MS ) - Base + 1
Power-on default [7:0] = 0x00h. Bit 7:0 Name DLM[7:0] R/W R/W Description Baud generator divisor high byte. Access only when LCR[7] is 1.
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5.2.1.5 Interrupt Enable Register - Base + 1
Power-on default [7:0] = 0x00h. Bit 7:4 3 2 1 Name Reserved EDSSI ELSI ETBFI R/W R/W R/W R/W R/W Description Return 0 when read. Access only when LCR[7] is 0 Enable Modem Status Interrupt. Access only when LCR[7] is 0. Enable Line Status Error Interrupt. Access only when LCR[7] is 0. Enable Transmitter Holding Register Empty Interrupt. Access only when LCR[7] is 0. 0 ERBFI R/W Enable Received Data Available Interrupt. Access only when LCR[7] is 0
5.2.1.6
Interrupt Identification Register - Base + 2
Power-on default [7:0] = 0x01h. Bit 7 Name FIFO_EN R/W R 0 : FIFO is disabled 1 : FIFO is enabled. 6 FIFO_EN R 0 : FIFO is disabled. 1 : FIFO is enabled. 5:4 3:1 Reserved IRQ_ID[2:0] R R Return 0 when read. 000 : Interrupt is caused by Modem Status 001 : Interrupt is caused by Transmitter Holding Register Empty 010 : Interrupt is caused by Received Data Available. 110 : Interrupt is caused by Character Timeout 011 : Interrupt is caused by Line Status.. 0 IRQ_PENDN R 1 : Interrupt is not pending. 0 : Interrupt is pending. Description
5.2.1.7
FIFO Control Register - Base + 2
Power-on default [7:0] = 0x00h. Bit 7:6 Name RCVR_TRIG[1:0] R/W W Description 00 : Receiver FIFO trigger level is 1. 01 : Receiver FIFO trigger level is 4. 10 : Receiver FIFO trigger level is 8.
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11 : Receiver FIFO trigger level is 14. 5:3 2 1 0 Reserved CLRTX CLRRX FIFO_EN W W W W 1 : Reset the transmitter FIFO. 1 : Reset the receiver FIFO. 0 : Disable FIFO 1 : Enable FIFO
5.2.1.8
Line Control Register - Base + 3
Power-on default [7:0] = 0x00h. Bit 7 Name DLAB R/W R/W Description 0 : Divisor Latch can't be accessed. 1 : Divisor Latch can be accessed via Base and Base+1. 6 SETBRK R/W 1 : Transmit a break condition. 0 : Transmitter is in normal condition. 5:3 STKPAR EPS PEN R/W XX0 : Parity Bit is disable 001 : Parity Bit is odd. 011 : Parity Bit is even 101 : Parity Bit is logic 1 111 : Parity Bit is logic 0 2 STB R/W 0 : Stop bit is one bit 1 : When word length is 5 bit stop bit is 1.5 bit else stop bit is 2 bit 1:0 WLS[1:0] R/W 00 : Word length is 5 bit 01 : Word length is 6 bit 10 : Word length is 7 bit 11 : Word length is 8 bit
5.2.1.9
MODEM Control Register - Base + 4
Power-on default [7:0] = 0x00h. Bit 7:5 4 Name Reserved LOOP R/W R/W R/W Return 0 when read. 0 : UART in normal condition. 1 : UART is internal loop back Description
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3 OUT2 R/W 0 : All interrupt is disable. 1 : Interrupt is enabled/disabled by IER. 2 1 OUT1 RTS R/W R/W Read from MSR[6] is loop back mode 0 : RTS# is forced to logic 1 1 : RTS# is forced to logic 0 0 DTR R/W 0 : DTR# is forced to logic 1 1 : DTR# is forced to logic 0
5.2.1.10 Line Status Register - Base + 5
Power-on default [7:0] = 0x60h. Bit 7 Name RCR_ERR R/W R Description 0 : No error in the FIFO when FIFO is enabled 1 : Error in the FIFO when FIFO is enabled. 6 TEMT R 0 : Transmitter is in transmitting. 1 : Transmitter is empty. 5 THRE R 0 : Transmitter Holding Register is not empty. 1 : Transmitter Holding Register is empty. 4 BI R 0 : No break condition detected. 1 : A break condition is detected. 3 FE R 0 : Data received has no frame error. 1 : Data received has frame error. 2 PE R 0 : Data received has no parity error. 1 : Data received has parity error. 1 OE R 0 : No overrun condition occur. 1 : A overrun condition occur. 0 DR R 0 : No data is ready for read. 1 : Data is received .
5.2.1.11 MODEM Status Register - Base + 6
Power-on default [7:0] = 0xX0h. Bit 7 DCD Name R/W R Description Complement of DCD# input. In loop back mode, this bit is equivalent to OUT2 in MCR. 6 RI R Complement of RI# input. In loop back mode , this bit is equivalent to
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OUT1 in MCR 5 DSR R Complement of DSR# input. In loop back mode , this bit is equivalent to DTR in MCR 4 CTS R Complement of CTS# input. In loop back mode , this bit is equivalent to RTS in MCR 3 DDCD R 0 : No state changed at DCD#. 1 : State changed at DCD#.
2
TERI
R
0 : No Trailing edge at RI#. 1 : A low to high transition at RI#.
1
DDSR
R
0 : No state changed at DSR#. 1 : State changed at DSR#.
0
DCTS
R
0 : No state changed at CTS#. 1 : State changed at CTS#.
5.2.1.11 Scratch Register - Base + 7
Power-on default [7:0] = 0x00h. Bit 7:0 Name SCR_DATA[7:0] R/W R/W Scratch register. Description
5.3
IR Function
The F81216AD infrared interface provides a two way wireless communications port using
infrared as the transmission medium. The IrDA 1.0 (SIR) is found in UART1 IrDA SIR specifies asynchronous serial communication at baud rate up to 115.2Kbps. Each byte is sent serial LSB first beginning with a zero value start bit. A zero is signaled by sending a single infrared pulse at the beginning of the serial bit time. A one is signaled by the absence of an infrared pulse during the bit time. IRTX acts as a transmit pin and IRRX acts as a receiving one. As for detail description, please refer to register description.
5.4
Watch Dog Timer Function
Watch dog timer is provided for system controlling. If time-out can trigger one signal to low
level, the signal default is tri-state (need external pull up resister). The time interval has three ways: One is the hardware power on setting to enable, timer set to 10 second (24MHz). If 48MHz clock input, the timer is set to 5 second.
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Two is programmed by registers. The other is set the base address into registers, and use the base address the control it. The timer unit has three kinds: 10mS, 1S, 1Min. 5.4.1 Watchdog Port Register
5.4.1.1
Timer Status and Control Register - Base + 0
Power-on default [7:0] = 0x02 when DTR3#/PS_WDT is pull-up, else 0x0. Bit 7:3 2:1 Name Reserved WDT_UNIT[1:0] R/W R/W R/W Return 0 when read. 00 : Timer Unit is 10ms. 01 : Timer Unit is 1 second 10 : Timer Unit is 1 minute. 11 : reserved. 0 WDT_EVENT R/W When read 0 : no time out occur. 1 : time out has occurred. when write 0 : no action 1 : clear the time out status. Description
5.4.1.2
Timer Count Number Register - Base + 1
Power-on default [7:0] = 0x0Ah when DTR3#/PS_WDT is pull-up , else 0x00h. Bit 7:0 Name WDT_CNT[7:0] R/W R/W Description The number of count for watchdog timer. Write the same value to enable the timer, write 0 to disable timer.
5.5
Serial IRQ
F81216AD supports a serial IRQ scheme. Because more than one device may need to The clock source is
share the signal serial IRQ signal line, an open drain signal scheme is used. the PCI clock.
The serial interrupt is transferred on the SERIRQ signal, one cycle consisting of
three frames types: a start frame, several IRQ/Data frame, and one Stop frame.
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5.5.1 Start Frame There are two modes of operation for the SERIRQ Start frame: Quiet mode and Continuous mode. In the Quiet mode, the peripheral drives the SERIRQ signal active low for one clock, and This brings all the states machines of the peripherals from idle to active states. This makes the total number of then tri-states it.
The host controller will then take over driving SERIRQ signal low in the next clock and will continue driving the SERIRQ low for programmable 3 to 7 clock periods. for one clock and then tri-states it. low for 4 to 8 clock periods. clocks low for 4 to 8 clock periods. After these clocks, the host controller will drive the SERIRQ high In the Continuous mode, only the host controller initiates the The host controller drives the SERIRQ signal START frame to update IRQ/Data line information. for the host controller to initiate the first Start frame. 5.5.2 IRQ/Data Frame Once the start frame has been initiated, all the peripherals must start counting frames based on the rising edge of the start pulse. low if the corresponding IRQ is active. left tri-stated. Each IRQ/Data Frame is three clocks: Sample phase, If the corresponding IRQ is inactive, then SERIRQ must be During Recovery phase, and Turn-around phase. During the Sample phase, the peripheral drives SERIRQ During the Recovery phase, the peripheral device drives the SERIRQ high.
Upon a reset, the SERIRQ signal is defaulted to the Continuous mode
the Turn-around phase, the peripheral device left the SERIRQ tri-stated. The IRQ/Data Frame has a number of specific order, as shown in Table 5-1. The F81216AD is only support IRQ3, IRQ4, IRQ5, IRQ9, IRQ10, and IRQ11.
Table 5-1 IRQSER Sampling periods IRQ/Data Frame 1 2 3 4 5 6 7 8 9 Signal Sampled IRQ0 IRQ1 SMI# IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 # of clocks past Start 2 5 8 11 14 17 20 23 26
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10 11 12 13 14 15 16 17 18 19 20 21 32:22 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 IOCHCK# INTA# INTB# INTC# INTD# Unassigned 29 32 35 38 41 44 47 50 53 56 59 62 95
5.5.3 Stop Frame After all IRQ/Data Frames have completed, the host controller will terminate SERIRQ by a Stop frame. clocks. mode. Only the host controller can initiate the Stop frame by driving SERIRQ low for 2 or 3 If the Stop Frame is low for 2 clocks, the next SERIRQ cycle's Sample mode is the Quiet If the Stop Frame is low for 3 clocks, the next SERIRQ cycle's Sample mode is the
Continuous mode.
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6. Register Description
Registers are programmed by port 0x4E(0x2E) and 0x4F(0x2F). 0x4E is the index port and 0x4F is the data port . RTS1#/PS_CONF_2E 0 (default) 1 Index Port 0x4E 0x2E Data Port 0x4F 0x2F
To enable configuration registers programming, entry key must output twice to index port continuously. The entry key is decided by power on setting pins RTS2#/PS_CONF_KEY1 and RTS3#/PS_CONF_KEY0 as following:
RTS2#/PS_CONF_KEY1 0 0 1 1
RTS3#/PS_CONF_KEY0 0 1 0 1
Entry key 0x77 ( default ) 0xA0 0x87 0x67
To exit configuration registers programming, output 0xAA to index port.
Global Control Registers "-" Reserved or Tri-State Global Control Registers Register 0x[HEX] 02 07 20 21 23 24 25 27 Register Name MSB Software Reset Register Logic Device Number Register (LDN) Chip ID Register Chip ID Register Vender ID Register Vender ID Register Clock Select Register Port Select Register 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 1/0 0 0 0 1 0 0 0 1 0 1 0 1 1/0 0 0 1/0 Default Value LSB 0 0 0 0 1 0 0 1/0
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Device Configuration Registers "-" Reserved or Tri-State UART1 Device Configuration Registers (LDN CR00) Register 0x[HEX] 30 60 61 70 F0 F1 F4 F5 Register Name MSB UART1 Device Enable Register Base Address High Register Base Address Low Register IRQ Channel Select Register Clock Select Register IR Control Register 9-bit Mode Slave Address Register 9-bit Mode Slave Address Mask Register 0 1/0 0 0 0 0 1/0 0 0 0 0 1/0 0 0 0 0 0 1/0 0 0 0 0 0 0 1/0 0 0 0 0 0 0 0 0 0 0 0 0 1/0 0 1/0 0 0 0 0 Default Value LSB 1/0 1/0 0 1/0 0 0 0 0
UART2 Device Configuration Registers (LDN CR01) Register 0x[HEX] 30 60 61 70 F0 F4 F5 Register Name MSB UART2 Device Enable Register Base Address High Register Base Address Low Register IRQ Channel Select Register Clock Select Register 9-bit Mode Slave Address Register 9-bit Mode Slave Address Mask Register 0 1/0 0 0 0 0 1/0 0 0 0 0 1/0 0 0 0 0 0 1/0 0 0 0 0 0 1/0 0 0 0 0 0 0 1/0 0 0 0 1/0 0 0 0 0 0 Default Value LSB 1/0 0 0 0 0 0 0
UART3 Device Configuration Registers (LDN CR02) Register 0x[HEX] 30 60 61 70 F0 F4 F5 Register Name MSB UART3Device Enable Register Base Address High Register Base Address Low Register IRQ Channel Select Register Clock Select Register 9-bit Mode Slave Address Register 9-bit Mode Slave Address Mask Register 0 1/0 0 0 0 0 1/0 0 0 0 0 1/0 0 0 0 0 0 0 0 0 0 0 0 1/0 0 0 0 0 0 0 1/0 0 0 0 1/0 0 0 0 0 0 Default Value LSB 1/0 1/0 0 1/0 0 0 0
UART4 Device Configuration Registers (LDN CR03) Register 0x[HEX] 30 60 Register Name MSB UART2 Device Enable Register Base Address High Register 0 0 0 0 0 0 1/0 Default Value LSB 1/0 0
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61 70 F0 F4 F5 Base Address Low Register IRQ Channel Select Register Clock Select Register 9-bit Mode Slave Address Register 9-bit Mode Slave Address Mask Register 1/0 0 0 0 1/0 0 0 0 1/0 0 0 0 0 0 0 0 0 0 1/0 1/0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1/0 0 0 0
WDT Device Configuration Registers (LDN CR08) Register 0x[HEX] 30 60 61 70 F0 F1 Register Name MSB UART2 Device Enable Register Base Address High Register Base Address Low Register IRQ Channel Select Register Timer Status and Control Register Timer Count Number Register 0 0 0 0 1/0 0 0 0 0 0 0 0 0 0 0 0 1/0 1/0 0 0 0 0 0 1/0 0 1/0 0 Default Value LSB 1/0 0 0 0 0 1/0
6.1.
6.1.1 Bit
Global Control Registers
Software Reset Register Index 02h Name R/W Default R/W 0 Reserved Write 1 to reset the register and device powered by VDD ( VCC ). Description
7-1 Reserved 0 SOFT_RST
6.1.2 Bit
Logic Device Number Register (LDN) Index 07h Name R/W Default R/W 00h Description 00h : Select UART 1 device configuration register 01h : Select UART 2 device configuration register 02h : Select UART 3 device configuration register 03h : Select UART 4 device configuration register 08h : Select Watchdog Timer device configuration register
7-0 LDN
6.1.3 Bit
Chip ID Register Index 20h Name R/W Default R 02h Chip ID 1 of F81216AD.. Description
7-0 CHIP_ID1
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6.1.4 Bit Chip ID Register Index 21h Name R/W Default R 16h Chip ID2 of F81216AD. Description
7-0 CHIP_ID2
6.1.5 Bit
Vendor ID Register Index 23h Name R/W Default R 19h Vendor ID 1 of Fintek devices. Description
7-0 VENDOR_ID1
6.1.6 Bit
Vendor ID Register Index 24h Name R/W Default R 34h Vendor ID 2 of Fintek devices. Description
7-0 VENDOR_ID2
6.1.7 Bit
Clock Select Register Index 25h Name R/W Default R/W 0 Reserved 1 : The CLKIN is 48MHz 0 : The CLKIN is 24MHz. This bit must program to indicate the frequency of the clock source, or the device will not function correctly. Port SelectRegister Index 27h Name R/W Default Reserved. The default value of this bit is decided by power on strap pin PS_CONF_2E. The default is "1" when PS_CONF_2E is low during power on. 0: The configuration port is 0x2E/0x2F. 1: The configuration port is 0x4E/0x4F. Description Description
7-1 Reserved 0 CLK_SEL
6.1.8 Bit
7-5 Reserved 4 PORT_4E_EN
3-2 Reserved
-
-
Reserved.
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1-0 ENTRY_KEY_SEL R/W 0 Configuration Entry Key Select. The default value of these bits are determined by PS_CONF_KEY1 and PS_CONF_KEY0. 00: The entry key is 0x77. 01: The entry key is 0xA0. 10: The entry key is 0x87. 11: The entry key is 0x67.
6.2.
UART1 Registers (CR00)
UART 1 Device Enable Register Index 30h
Bit
Name
R/W Default R/W Reserved 0: disable UART 1. 1: enable UART 1.
Description
7-1 Reserved 0 UR1_EN
This bit is determined by SOUT1/PS_3F8_IRQA or DTR1#/PS_3E0_IRQA. The power value will "1" if an external pull up resistor is attached to SOUT1/PS_3F8_IRQA or DTR1#/PS_3E0_IRQA. Otherwise, the power on value will be "0".
Base Address High Register Index 60h
Bit
Name
R/W Default R/W -
Description The MSB of UART 1 base address. This byte is determined by SOUT1/PS_3F8_IRQA or DTR1#/PS_3E0_IRQA. The power on default is 0x03 if SOUT1/PS_3F8_IRQA or DTR1#/PS_3E0_IRQA is pull up. Otherwise, it is 0x00.
7-0 BASE_ADDR_HI
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Base Address Low Register Index 61h
Bit
Name
R/W Default R/W -
Description The LSB of UART 1 base address. This byte is determined by SOUT1/PS_3F8_IRQA or DTR1#/PS_3E0_IRQA. The power on default is 0xF8 if SOUT1/PS_3F8_IRQA is pull up. It is 0xE0 if DTR1#/PS_3E0_IRQA is pull up. Otherwise, it is 0x00.
7-0 BASE_ADDR_LO
IRQ Channel Select Register Index 70h
Bit
Name
R/W Default R/W 0 Reserved. 0 : PCI IRQ sharing mode. 1 : ISA IRQ sharing mode.
Description
7-6 Reserved 5 URAIRQ_MODE
This bit is effective in IRQ sharing mode. 4 URAIRQ_SHAR R/W 0 0 : IRQ is not sharing with other device. 1 : IRQ is sharing with other device. 3-0 SELUR1IRQ R/W Select the IRQ channel for UART 1. This byte is determined by SOUT1/PS_3F8_IRQA or DTR1#/PS_3E0_IRQA. The power on default is 0x03 if SOUT1/PS_3F8_IRQA or DTR1#/PS_3E0_IRQA is pull up. Otherwise, it is 0x00.
RS485 Enable Register Index F0h
Bit 7
Name 9BIT_MODE_URA
R/W Default R/W 0 0: normal UART function
Description
1: enable 9-bit mode (multi-drop mode). In the 9-bit mode, the parity bit becomes the address/data bit.. 6 AUTO_ADDR_URA R/W 0 This bit works only in 9-bit mode. 0: the SM2 bit will be cleared by host, so that data could be received. 1: the SM2 bit will be cleared by hardware according to the sent address and the given address (or broadcast address derived by SADDR_URA and SADEN_URA)
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5 RTS_Invert R/W 0 0: Default non function 1: When RS485_URA set to 1, RTS# signal will be inverted when assert out. 4 RS485_URA R/W 0 0: RS232 mode 1: RS485 mode, which will auto assert RTS# (RTS# is low) when receiving is required.. 3 RXW4C_IRA R/W 0 0 : No reception delay when SIR is changed from TX to RX. 1 : Reception delay 4 character-time when SIR is changed from TX to RX. 2 TXW4C_IRA R/W 0 0 : No transmission delay when SIR is changed from RX to TX. 1 : Transmission delay 4 character-time when SIR is changed from RX to TX. 1-0 SELURACLK1 SELURACLK0 R/W 00 00: UART 1 clock source is 1.8462MHz ( 24MHz/13 ) 01: UART 1 clock source is 18MHz. 10: UART 1 clock source is 24MHz. 11: UART 1 clock source is 14MHz.
IR Control Register Index F1h
Bit
Name
R/W Default R R/W 00 Return 010b when read. 0X: Disable IR1 function.
Description
7-5 Reserved 4-3 IRA_MODE1 IRA_MODE0
10 : Enable IR1 function, active pulse is 1.6uS. 11 : Enable IR1 function, active pulse is 3/16 bit time.
2
Half_Full_Duplex
R/W
0
0 : Full Duplex function for IR self test. 1 : Half Duplex function. Return 1 when read.
1
TXINV_IRA
R/W
0
0 : IRTX1 is not inversed. 1 : Inverse the IRTX1.
0
RXINV_IRA
R/W
0
0 : IRRX1 is not inversed. 1 : Inverse the IRRX1.
9-bit Mode Slave Address Register Index F4h
Bit
Name
R/W Default
Description
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7-0 SADDR_URA R/W 00h This byte accompanying with SADEN_URA will determine the given address and broadcast address in 9-bit mode. The UART will response to both given and broadcast address. Follow the description to determine the given address and broadcast address: 1. given address: If bit n of SADEN_URA is "0", then the corresponding bit of SADDR_URA is don't care. 2. broadcast address: If bit n of ored SADDR_URA and SADEN_URA is "0", don't care that bit. The remaining bit which is "1" is compared to the received address. Ex. SADDR_URA SADEN_URA Given Address Broadcast Address 0101_1100b 1111_1001b 0101_1xx0b 1111_11x1b
9-bit Mode Slave Address Mask Register Index F5h
Bit
Name
R/W Default R/W 00h
Description This byte accompanying with SADDR_URA will determine the given address and broadcast address in 9-bit mode. The UART_URA will response to both given and broadcast address. Follow the description to determine the given address and broadcast address: 1. given address: If bit n of SADEN_URA is "0", then the corresponding bit of
7-0 SADEN_URA
SADDR_URA is don't care. 1. broadcast address: If bit n of ored SADDR_URA and SADEN_URA is "0", don't care that bit. The remaining bit which is "1" is compared to the received address. Ex. SADDR_URA SADEN_URA Given Address Broadcast Address 0101_1100b 1111_1001b 0101_1xx0b 1111_11x1b
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6.3. UART2 Registers (CR01)
UART 2 Device Enable Register Index 30h
Bit
Name
R/W Default R/W Reserved 0: disable UART 2. 1: enable UART 2.
Description
7-1 Reserved 0 UR2_EN
This bit is determined by SOUT2/PS_2F8_IRQB or DTR2#/PS_2E0_IRQB. The power value will "1" if an external pull up resistor is attached to SOUT2/PS_2F8_IRQB or DTR2#/PS_2E0_IRQB. Otherwise, the power on value will be "0".
Base Address High Register Index 60h
Bit
Name
R/W Default R/W -
Description The MSB of UART 2 base address. This byte is determined by SOUT2/PS_2F8_IRQB or DTR2#/PS_2E0_IRQB. The power on default is 0x02 if SOUT2/PS_2F8_IRQB or DTR2#/PS_2E0_IRQB is pull up. Otherwise, it is 0x00.
7-0 BASE_ADDR_HI
Base Address Low Register Index 61h
Bit
Name
R/W Default R/W -
Description The LSB of UART 2 base address. This byte is determined by SOUT2/PS_2F8_IRQB or DTR2#/PS_2E0_IRQB. The power on default is 0xF8 if SOUT2/PS_2F8_IRQB is pull up. It is 0xE0 if DTR2#/PS_2E0_IRQB is pull up. Otherwise, it is 0x00.
7-0 BASE_ADDR_LO
IRQ Channel Select Register Index 70h
Bit
Name
R/W Default Reserved.
Description
7-6 Reserved
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5 URBIRQ_MODE R/W 0 0 : PCI IRQ sharing mode. 1 : ISA IRQ sharing mode. This bit is effective in IRQ sharing mode. 4 URBIRQ_SHAR R/W 0 0 : IRQ is not sharing with other device. 1 : IRQ is sharing with other device. 3-0 SELUR2IRQ R/W Select the IRQ channel for UART 2. This byte is determined by SOUT2/PS_2F8_IRQB or DTR2#/PS_2E0_IRQB. The power on default is 0x04 if SOUT2/PS_2F8_IRQB or DTR2#/PS_2E0_IRQB is pull up. Otherwise, it is 0x00.
RS485 Enable Register Index F0h
Bit 7
Name 9BIT_MODE_URB
R/W Default R/W 0 0: normal UART function
Description
1: enable 9-bit mode (multi-drop mode). In the 9-bit mode, the parity bit becomes the address/data bit.. 6 AUTO_ADDR_URB R/W 0 This bit works only in 9-bit mode. 0: the SM2 bit will be cleared by host, so that data could be received. 1: the SM2 bit will be cleared by hardware according to the sent address and the given address (or broadcast address derived by SADDR_URB and SADEN_URB) 5 RTS_Invert R/W 0 0: Default non function 1: When RS485_URA set to 1, RTS# signal will be inverted when assert out. 4 RS485_URB R/W 0 0: RS232 mode 1: RS485 mode, which will auto assert RTS# (RTS# is low) when receiving is required.. 3-2 Reserved 1-0 SELURBCLK1 SELURBCLK0 R/W R/W 0 00 Dummy Registers 00: UART 2 clock source is 1.8462MHz ( 24MHz/13 ) 01: UART 2 clock source is 18MHz. 10: UART 2 clock source is 24MHz. 11: UART 2 clock source is 14MHz.
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9-bit Mode Slave Address Register Index F4h
Bit
Name
R/W Default R/W 00h
Description This byte accompanying with SADEN_URB will determine the given address and broadcast address in 9-bit mode. The UART will response to both given and broadcast address. Follow the description to determine the given address and broadcast address: 3. given address: If bit n of SADEN_URB is "0", then the corresponding bit of SADDR_URB is don't care. 4. broadcast address: If bit n of ored SADDR_URB and SADEN_URB is "0", don't care that bit. The remaining bit which is "1" is compared to the received address. Ex. SADDR_URB SADEN_URB Given Address Broadcast Address 0101_1100b 1111_1001b 0101_1xx0b 1111_11x1b
7-0 SADDR_URB
9-bit Mode Slave Address Mask Register Index F5h
Bit
Name
R/W Default R/W 00h
Description This byte accompanying with SADDR_URB will determine the given address and broadcast address in 9-bit mode. The UART_URB will response to both given and broadcast address. Follow the description to determine the given address and broadcast address: 1. given address: If bit n of SADEN_URB is "0", then the corresponding bit
7-0 SADEN_URB
of SADDR_URB is don't care. 2. broadcast address: If bit n of ored SADDR_URB and SADEN_URB is "0", don't care that bit. The remaining bit which is "1" is compared to the received address. Ex. SADDR_URB SADEN_URB Given Address Broadcast Address 0101_1100b 1111_1001b 0101_1xx0b 1111_11x1b
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6.4. UART3 Registers (CR02)
UART 3 Device Enable Register Index 30h
Bit
Name
R/W Default R/W Reserved 0: disable UART 3. 1: enable UART 3.
Description
7-1 Reserved 0 UR3_EN
This bit is determined by SOUT3/PS_3E8_IRQC. The power value will "1" if an external pull up resistor is attached to SOUT3/PS_3E8_IRQC. Otherwise, the power on value will be "0".
Base Address High Register Index 60h
Bit
Name
R/W Default R/W -
Description The MSB of UART 3 base address. This byte is determined by SOUT3/PS_3E8_IRQC. The power on default is 0x03 if SOUT3/PS_3E8_IRQC is pull up. Otherwise, it is 0x00.
7-0 BASE_ADDR_HI
Base Address Low Register Index 61h
Bit
Name
R/W Default R/W -
Description The LSB of UART 3 base address. This byte is determined by SOUT3/PS_3E8_IRQC. The power on default is 0xE8 if SOUT3/PS_3E8_IRQC is pull up. Otherwise, it is 0x00.
7-0 BASE_ADDR_LO
IRQ Channel Select Register Index 70h
Bit
Name
R/W Default R/W 0 Reserved. 0 : PCI IRQ sharing mode. 1 : ISA IRQ sharing mode.
Description
7-6 Reserved 5 URCIRQ_MODE
This bit is effective in IRQ sharing mode.
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4 URCIRQ_SHAR R/W 0 0 : IRQ is not sharing with other device. 1 : IRQ is sharing with other device. 3-0 SELUR3IRQ R/W Select the IRQ channel for UART 3. This byte is determined by SOUT3/PS_3E8_IRQC. The power on default is 0x05 if SOUT3/PS_3E8_IRQC is pull up. Otherwise, it is 0x00.
RS485 Enable Register Index F0h
Bit 7
Name 9BIT_MODE_URC
R/W Default R/W 0 0: normal UART function
Description
1: enable 9-bit mode (multi-drop mode). In the 9-bit mode, the parity bit becomes the address/data bit.. 6 AUTO_ADDR_URC R/W 0 This bit works only in 9-bit mode. 0: the SM2 bit will be cleared by host, so that data could be received. 1: the SM2 bit will be cleared by hardware according to the sent address and the given address (or broadcast address derived by SADDR_URC and SADEN_URC) 5 RTS_Invert R/W 0 0: Default non function 1: When RS485_URA set to 1, RTS# signal will be inverted when assert out. 4 RS485_URC R/W 0 0: RS232 mode 1: RS485 mode, which will auto assert RTS# (RTS# is low) when receiving is required.. 3-2 Reserved 1-0 SELURCCLK1 SELURCCLK0 R/W R/W 0 00 Dummy Registers 00: UART 3 clock source is 1.8462MHz ( 24MHz/13 ) 01: UART 3 clock source is 18MHz. 10: UART 3 clock source is 24MHz. 11: UART 3 clock source is 14MHz.
9-bit Mode Slave Address Register Index F4h
Bit
Name
R/W Default
Description
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7-0 SADDR_URC R/W 00h This byte accompanying with SADEN_URC will determine the given address and broadcast address in 9-bit mode. The UART will response to both given and broadcast address. Follow the description to determine the given address and broadcast address: 5. given address: If bit n of SADEN_URC is "0", then the corresponding bit of SADDR_URC is don't care. 6. broadcast address: If bit n of ored SADDR_URC and SADEN_URC is "0", don't care that bit. The remaining bit which is "1" is compared to the received address. Ex. SADDR_URC SADEN_URC Given Address Broadcast Address 0101_1100b 1111_1001b 0101_1xx0b 1111_11x1b
9-bit Mode Slave Address Mask Register Index F5h
Bit
Name
R/W Default R/W 00h
Description This byte accompanying with SADDR_URC will determine the given address and broadcast address in 9-bit mode. The UART_URC will response to both given and broadcast address. Follow the description to determine the given address and broadcast address: 1. given address: If bit n of SADEN_URC is "0", then the corresponding bit
7-0 SADEN_URC
of SADDR_URC is don't care. 3. broadcast address: If bit n of ored SADDR_URC and SADEN_URC is "0", don't care that bit. The remaining bit which is "1" is compared to the received address. Ex. SADDR_URC SADEN_URC Given Address Broadcast Address 0101_1100b 1111_1001b 0101_1xx0b 1111_11x1b
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6.5. UART4 Registers (CR03)
UART 4 Device Enable Register Index 30h
Bit
Name
R/W Default R/W Reserved 0: disable UART 4. 1: enable UART 4.
Description
7-1 Reserved 0 UR4_EN
This bit is determined by SOUT4/PS_2E8_IRQD. The power value will "1" if an external pull up resistor is attached to SOUT4/PS_2E8_IRQD. Otherwise, the power on value will be "0".
Base Address High Register Index 60h
Bit
Name
R/W Default R/W -
Description The MSB of UART 4 base address. This byte is determined by SOUT4/PS_2E8_IRQD. The power on default is 0x02 if SOUT4/PS_2E8_IRQD is pull up. Otherwise, it is 0x00.
7-0 BASE_ADDR_HI
Base Address Low Register Index 61h
Bit
Name
R/W Default R/W -
Description The LSB of UART 4 base address. This byte is determined by SOUT4/PS_2E8_IRQD. The power on default is 0xE8 if SOUT4/PS_2E8_IRQD is pull up. Otherwise, it is 0x00.
7-0 BASE_ADDR_LO
IRQ Channel Select Register Index 70h
Bit
Name
R/W Default R/W 0 Reserved. 0 : PCI IRQ sharing mode. 1 : ISA IRQ sharing mode.
Description
7-6 Reserved 5 URDIRQ_MODE
This bit is effective in IRQ sharing mode.
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4 URDIRQ_SHAR R/W 0 0 : IRQ is not sharing with other device. 1 : IRQ is sharing with other device. 3-0 SELUR4IRQ R/W Select the IRQ channel for UART 4. This byte is determined by SOUT4/PS_2E8_IRQD. The power on default is 0x09 if SOUT4/PS_2E8_IRQD is pull up. Otherwise, it is 0x00.
RS485 Enable Register Index F0h
Bit 7
Name 9BIT_MODE_URD
R/W Default R/W 0 0: normal UART function
Description
1: enable 9-bit mode (multi-drop mode). In the 9-bit mode, the parity bit becomes the address/data bit.. 6 AUTO_ADDR_URD R/W 0 This bit works only in 9-bit mode. 0: the SM2 bit will be cleared by host, so that data could be received. 1: the SM2 bit will be cleared by hardware according to the sent address and the given address (or broadcast address derived by SADDR_URD and SADEN_URD) 5 RTS_Invert R/W 0 0: Default non function 1: When RS485_URA set to 1, RTS# signal will be inverted when assert out. 4 RS485_URD R/W 0 0: RS232 mode 1: RS485 mode, which will auto assert RTS# (RTS# is low) when receiving is required.. 3-2 Reserved 1-0 SELURDCLK1 SELURDCLK0 R/W R/W 0 00 Dummy Registers 00: UART 4 clock source is 1.8462MHz ( 24MHz/13 ) 01: UART 4 clock source is 18MHz. 10: UART 4 clock source is 24MHz. 11: UART 4 clock source is 14MHz.
9-bit Mode Slave Address Register Index F4h
Bit
Name
R/W Default
Description
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7-0 SADDR_URD R/W 00h This byte accompanying with SADEN_URD will determine the given address and broadcast address in 9-bit mode. The UART will response to both given and broadcast address. Follow the description to determine the given address and broadcast address: 7. given address: If bit n of SADEN_URD is "0", then the corresponding bit of SADDR_URD is don't care. 8. broadcast address: If bit n of ored SADDR_URD and SADEN_URD is "0", don't care that bit. The remaining bit which is "1" is compared to the received address. Ex. SADDR_URD SADEN_URD Given Address Broadcast Address 0101_1100b 1111_1001b 0101_1xx0b 1111_11x1b
9-bit Mode Slave Address Mask Register Index F5h
Bit
Name
R/W Default R/W 00h
Description This byte accompanying with SADDR_URD will determine the given address and broadcast address in 9-bit mode. The UART_URD will response to both given and broadcast address. Follow the description to determine the given address and broadcast address: 1. given address: If bit n of SADEN_URD is "0", then the corresponding bit
7-0 SADEN_URD
of SADDR_URD is don't care. 4. broadcast address: If bit n of ored SADDR_URD and SADEN_URD is "0", don't care that bit. The remaining bit which is "1" is compared to the received address. Ex. SADDR_URD SADEN_URD Given Address Broadcast Address 0101_1100b 1111_1001b 0101_1xx0b 1111_11x1b
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6.6. Watchdog Timer Registers (CR08)
Device Enable Register Index 30h
Bit
Name
R/W Default R/W 0 Reserved
Description
7-1 Reserved 0 WDT_EN
0: disable WDT. 1: enable WDT. This bit is determined by DTR3#/PS_WDT. The power value will "1" if an external pull up resistor is attached to DTR3#/PS_WDT. Otherwise, the power on value will be "0".
Base Address High Register Index 60h
Bit
Name
R/W Default R/W -
Description The MSB of UART 3 base address. This byte is determined by DTR3#/PS_WDT. The power on default is 0x04 if SOUT3/PS_3E8_IRQC is pull up. Otherwise, it is 0x00.
7-0 BASE_ADDR_HI
Base Address Low Register Index 61h
Bit
Name
R/W Default R/W -
Description The LSB of UART 3 base address. This byte is determined by DTR3#/PS_WDT. The power on default is 0x42 if DTR3#/PS_WDT is pull up. Otherwise, it is 0x00.
7-0 BASE_ADDR_LO
IRQ Channel Select Register Index 70h
Bit
Name
R/W Default R/W 0 Reserved. 0 : Disable WDT IRQ. 1 : Enable WDT IRQ.
Description
7-5 Reserved 4 WDTIRQ_EN
3-0 SELWDTIRQ
R/W
0h
Select the IRQ channel for WDT.
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Timer Status and Control Register Index F0h
Bit
Name
R/W Default R/W Reserved 00 : Timer Unit is 10ms. 01 : Timer Unit is 1 second 10 : Timer Unit is 1 minute.
Description
7-3 Reserved 2-1 WDT_UNIT
11 : reserved. This register is determined by DTR3#/PS_WDT. The power on default is 0x01 if DTR3#/PS_WDT is pull up. Otherwise, it is 0x00. 0 WDT_EVENT R/W 0 0 : no time out occur. 1 : time out has occurred. Write "1" to this bit will clear the status.
Timer Count Number Register Index F1h
Bit
Name
R/W Default R/W -
Description The number of count for watchdog timer. Write the same non-zero value twice to enable the timer, otherwise will disable timer. This register is determined by DTR3#/PS_WDT. The power on default is 0x0A if DTR3#/PS_WDT is pull up. Otherwise, it is 0x00.
7-0 WDT_CNT
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7. Electron Characteristic
7.1 Absolute Maximum Ratings
RATING -0.5 to 4.0 -0.5 to 5.5 0 to +70 -55 to +150 UNIT V V C C
PARAMETER Power Supply Voltage Input Voltage Operating Temperature Storage Temperature
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
7.2 DC Characteristics
((Ta = 0 C to 70 C, VDD = 3.3V 10%, VSS = 0V) PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS
I/O12t - TTL level bi-directional pin with source-sink capability of 12 mA Input Low Voltage Input High Voltage Output Low Current Output High Current Input High Leakage Input Low Leakage VIL VIH IOL IOH ILIH ILIL 2.0 10 12 -12 -10 +10 -10 0.8 V V mA mA A A VOL = 0.4V VOH = 2.4V VIN = VDD VIN = 0V
I/O12ts - TTL level bi-directional pin with source-sink capability of 12 mA and schmitt-trigger level input Input Low Threshold Voltage Input High Threshold Voltage Output Low Current Output High Current Input High Leakage Input Low Leakage VtVt+ IOL IOH ILIH ILIL 0.5 1.6 10 0.8 2.0 12 -12 -10 +10 -10 1.1 2.4 V V mA mA A A VDD = 3.3 V VDD = 3.3 V VOL = 0.4 V VOH = 2.4V VIN = VDD VIN = 0V
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PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS OUT12t - TTL level output pin with source-sink capability of 12 mA Output Low Current Output High Current IOL IOH 12 16 -14 -12 mA mA VOL = 0.4V VOH = 2.4V
OD8 - Open-drain output pin with sink capability of 8 mA Output Low Current IOL 6 8 mA VOL = 0.4V
OD16 - Open-drain output pin with sink capability of 16 mA Output Low Current IOL 12 16 mA VOL = 0.4V
I/OOD16ts - TTL level bi-directional pin, can select to OD or OUT by register, with 16 mA source-sink capability Input Low Threshold Voltage Input High Threshold Voltage Output Low Current Output High Current Input High Leakage Input Low Leakage INt - TTL level input pin Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage VIL VIH ILIH ILIL 2.0 +10 -10 0.8 V V A A VIN = VDD VIN = 0 V VtVt+ IOL IOH ILIH ILIL 0.5 1.6 6 0.8 2.0 8 -16 -12 +10 -10 1.1 2.4 V V mA mA A A VDD = 3.3 V VDD = 3.3 V VOL = 0.4 V VOH = 2.4V VIN = VDD VIN = 0V
INts - TTL level Schmitt-triggered input pin Input Low Threshold Voltage Input High Threshold Voltage Input High Leakage Input Low Leakage VtVt+ ILIH ILIL 0.5 1.6 0.8 2.0 1.1 2.4 +10 -10 V V A A VDD = 3.3V VDD = 3.3V VIN = VDD VIN = 0 V
8. Ordering Information
Part Number F81216AD Package Type 48 pin LQFP (Green Package) Production Flow Commercial, 0C to +70C
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9. Package Dimensions
48pin-LQFP
HD D
36 25
Dimension in inch
Dimension in mm Min.
--0.05 1.35 0.17 0.09
Symbol
Min.
Nom.
Max.
Nom.
----1.40 0.20 --7.00 7.00 0.50 9.00 9.00
Max.
1.60 0.15 1.45 0.27 0.20
37
24
E
HE
48
13
1
e
b
12
A A1 A2 b c D E e HD HE L L1 y 0
Notes:
c
0.45
0.60 1.00
0.75
--0
0.08 3.5
--7
A2
A
Seating Plane
See Detail F
A1 y
L L1 Detail F
1. Dimensions D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Millimeters 4. General appearance spec. should be based on final visual inspection spec.
Feature Integration Technology Inc.
Headquarters 3F-7, No 36, Tai Yuan St., Chupei City, Hsinchu, Taiwan 302, R.O.C. TEL : 886-3-5600168 FAX : 886-3-5600166 www: http://www.fintek.com.tw Taipei Office Bldg. K4, 7F, No.700, Chung Cheng Rd., Chungho City, Taipei, Taiwan 235, R.O.C. TEL : 866-2-8227-8027 FAX : 866-2-8227-8037
Please note that all datasheet and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this datasheet belong to their respective owner
-38-
July, 2008
V0.20P
10. Application Circuit
(Power On Setting Pin)
VCC3V RTS1# DTR1# SOUT1 RI1# CTS1# DSR1# SIN1 DCD1# IRRX IRTX
R2 4.7K PIN_18
R3 4.7K PIN_23
R4 4.7K PIN_24
R5 4.7K PIN_26
R6 4.7K PIN_33
R7 4.7K PIN_34
R8 4.7K PIN_36
R9 4.7K PIN_41
R10 4.7K PIN_42 R20 1k
R11 4.7K PIN_44 R21 1k
PIN_48 PIN_47 PIN_46 PIN_45 PIN_44 PIN_43 PIN_42 PIN_41 PIN_40 PIN_39
PIN_38 PIN_37 R12 DCD2# SIN2 DSR2# CTS2# RI2# SOUT2 DTR2# RTS2# 1k R13 1k R14 1k R15 1k R16 1k R17 1k R18 1k R19 1k
VCC3V R1 4.7K U1 48 47 46 45 44 43 42 41 40 39 38 37 IRTX IRRX RI1# DCD1# SOUT1 SIN1 DTR1# RTS1# DSR1# CTS1# RI2# DCD2#
R2 on and R12 off: UART 4 addr:0x2e8 IRQ9; off:UART 4 disabled. R5 on and R15 off: UART 3 addr:0x3e8 IRQ5; off:UART 3 disabled. R8 on and R18 off: UART 2 addr:0x2f8 irq4; R7 on, R17 off and R8 off, R18 on : UART 2 addr:0x2e0 IRQ4; R7 off, R17 on and R8 off, R18 on:UART 2 disabled. R11 on and R21 off: UART 1 addr:0x3f8 irq3; R10 on, R20 off and R11 off, R21 on: UART 1 addr:0x3e0 IRQ3; R10 off, R20 on and R11 off, R21 on:UART 1 disabled.
PCIRST# WDT_OUT# LAD3 LAD2 LAD1 LAD0 PCICLK LFRAME# SERIRQ CLK24IN
PIN_1 PIN_2
1 2 PIN_3 3 PIN_4 4 PIN_5 5 PIN_6 6 PIN_7 7 PIN_8 8 PIN_9 9 PIN_10 10 PIN_11 11 PIN_12 VCC3V 12 C2 0.1U
PCIRST# WDT_OUT# GND LAD3 LAD2 LAD1 LAD0 LCLK LFRAM# SERIRQ VCC CLKIN
216AD
F81216D
SOUT2 SIN2 DTR2# RTS2# DSR2# CTS2# VCC GND RI3# DCD3# SOUT3 SIN3
36 35 34 33 32 31 30 29 28 27 26 25
PIN_36 PIN_35 PIN_34 PIN_33 PIN_32 PIN_31 PIN_30 PIN_29 PIN_28 PIN_27 PIN_26 PIN_25
VCC3V
13 14 15 16 17 18 19 20 21 22 23 24
CTS4# DSR4# RTS4# DTR4# SIN4 SOUT4 DCD4# RI4# CTS3# DSR3# RTS3# DTR3#
C1 0.1U
R4 on and R14 off: Watch Dog Timer enabled and setting to 10 second when the clock input is 24Mhz. If the clock input is 48Mhz , the timer is setting to 5 second. off :disabled.
PIN_13 PIN_14 PIN_15 PIN_16 PIN_17 PIN_18 PIN_19 PIN_20 PIN_21 PIN_22 PIN_23 PIN_24
R16 is 0 when R6=1, R16 is 1 when R6=0. R13 is 0 when R3=1, R13 is 1 when R3=0. R19 is 0 when R9=1, R19 is 1 when R9=0.
RTS4# DTR4# SOUT4 RI4# CTS4# DSR4# SIN4 DCD4#
DCD3# SIN3 DSR3# CTS3# RI3# SOUT3 DTR3# RTS3#
R6
R3
R9
Address
Entry Key
On:1
0
0
0
0x4e/0x4f
0x77
Off:0
0
0
1
0x2e/0x2f
0x77
0
1
0
0x4e/0x4f
0xa0
0
1
1
0x2e/0x2f
0xa0
1
0
0
0x4e/0x4f
0x87
1
0
1
0x2e/0x2f
0x87
1
1
0
0x4e/0x4f
0x67
1
1
1
0x2e/0x2f
0x67
Title Feature Integration Technology Inc. Size B Date: Document Number F81216D Tuesday , January 10, 2006 Sheet 1 of 2 Rev 0.21
U2 VCC5V RTS1# DTR1# C3 0.1USOUT1 RI1# CTS1# DSR1# SIN1 DCD1# 20 16 15 13 19 18 17 14 12 11 VCC DA1 DA2 DA3 RY 1 RY 2 RY 3 RY 4 RY 5 GND RS232 (SOP20) +12V DY 1 DY 2 DY 3 RA1 RA2 RA3 RA4 RA9 -12V 1 5 6 8 2 3 4 7 9 10 +12V RTS1 DTR1 SOUT1RI1 CTS1 DSR1 SIN1DCD1 -12V P1 RI1 DTR1 CTS1 SOUT1RTS1 SIN1DSR1 DCD1 5 9 4 8 3 7 2 6 1 DB9 VCC5V RTS3# DTR3# SOUT3 C4 0.1U RI3# CTS3# DSR3# SIN3 DCD3# 20 16 15 13 19 18 17 14 12 11
U3 VCC DA1 DA2 DA3 RY 1 RY 2 RY 3 RY 4 RY 5 GND RS232 (SOP20) +12V DY 1 DY 2 DY 3 RA1 RA2 RA3 RA4 RA9 -12V 1 5 6 8 2 3 4 7 9 10 +12V RTS3 DTR3 SOUT3RI3 CTS3 DSR3 SIN3DCD3 -12V P2 RI3 DTR3 CTS3 SOUT3RTS3 SIN3DSR3 DCD3 5 9 4 8 3 7 2 6 1 DB9
(UART1)
(UART3)
U4 VCC5V RTS2# DTR2# SOUT2 C5 0.1U RI2# CTS2# DSR2# SIN2 DCD2# 20 16 15 13 19 18 17 14 12 11 VCC DA1 DA2 DA3 RY 1 RY 2 RY 3 RY 4 RY 5 GND RS232 (SOP20) +12V DY 1 DY 2 DY 3 RA1 RA2 RA3 RA4 RA9 -12V 1 5 6 8 2 3 4 7 9 10 +12V RTS2 DTR2 SOUT2RI2 CTS2 DSR2 SIN2DCD2 -12V P3 RI2 DTR2 CTS2 SOUT2RTS2 SIN2DSR2 DCD2 5 9 4 8 3 7 2 6 1 DB9 VCC5V RTS4# DTR4# SOUT4 RI4# C6 0.1U CTS4# DSR4# SIN4 DCD4# 20 16 15 13 19 18 17 14 12 11
U5 VCC DA1 DA2 DA3 RY 1 RY 2 RY 3 RY 4 RY 5 GND RS232 (SOP20) +12V DY 1 DY 2 DY 3 RA1 RA2 RA3 RA4 RA9 -12V 1 5 6 8 2 3 4 7 9 10 +12V RTS4 DTR4 SOUT4RI4 CTS4 DSR4 SIN4DCD4 -12V P4 RI4 DTR4 CTS4 SOUT4RTS4 SIN4DSR4 DCD4 5 9 4 8 3 7 2 6 1 DB9
(UART2)
(UART4)
VCC3V
JP1 1 2 3 4 5 C7 0.1U HEADER 5
IRRX IRTX
(IrDA)
Title Feature Integration Technology Inc. Size B Date: Document Number UART Tuesday , January 10, 2006 Sheet 2 of 2 Rev 0.2

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